The ever-increasing use of microprocessors has led to the development of a new data processing system architecture that allows a plurality of microprocessors to communicate with one another at high speed through a shared storage. This involves the use of a common bus over which the microprocessors and the storage can exchange data, addresses and various control signals. Since the common bus can only be used by one microprocessor at a time, it is essential that such data processing systems be provided with suitable means for controlling access to the common bus by the microprocessors so as to prevent simultaneous accesses as these would result in errors. A great many arbitration devices for resolving competing requests for access to a shared resource exist in the prior art, and it would be tedious to enumerate them here.
A disadvantage of some of these prior art devices in that, in many cases, they are designed to meet the requirements of specific processors or resources and are consequently difficult to use with other processors or resources.
A drawback to other prior art arbitration devices is that they are intended to resolve contentions likely to arise in connection with most applications and in most foreseeable situations and are, as a result, somewhat complex. While this complexity may be justified in the case of particularly involved applications, its effect is to reduce the speed of the devices and to make them poorly suited to the requirements of less intricate applications in which priorities among the processors may be unnecessary or, if needed at all, can be quite simple.